1. Field of the Invention
The present invention relates to hardware-assisted virtualization of data processing resources. More particularly, the invention concerns improvements in providing multiple layers of hardware-assisted virtualization.
2. Description of the Prior Art
By way of background, modern microprocessors, such as those based on the x86 architecture, include hardware-assisted support for virtualization. A set of virtualization instructions allows a hypervisor to operate in a super-privileged root mode while running guest operating systems and application software in non-root mode at their normal privilege levels. The x86 hardware virtualization feature is presently not virtualized itself. This may prevent an x86 root-mode hypervisor from efficiently running a non-root mode hypervisor as a guest, a concept known as nested or layered virtualization. The two main techniques to address this shortcoming are trap-and-emulate and dynamic translation. Trap-and-emulate involves the hardware trapping individual virtualization instructions issued by the guest hypervisor and having the root-mode hypervisor emulate their behavior. The high frequency of virtualization instructions in the critical code paths can make this mechanism prohibitively slow. Dynamic translation involves translating the guest hypervisor's privileged code sequences to instructions that are safely confined within the guest virtual machine. This is complicated and may have an unacceptably high performance impact on certain workloads.